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TPS7A52

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SBVS295 – NOVEMBER 2019

Product Folder Links: TPS7A52

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Copyright © 2019, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 Recommended Capacitor Types

The TPS7A52 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry

standard for these types of applications and are recommended, but must be used with good judgment. Ceramic

capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability

across temperature. The use of Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. Make sure to derate ceramic capacitors by at least 50%. The input and output capacitors

consideration.

The TPS7A52 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 µF or

greater of capacitance) at the output and 10 µF or greater (5 µF or greater of capacitance) at the input. Use at

least a 47-µF capacitor at the input to minimize input impedance. Place the input and output capacitors as near

as practical to the respective input and output pins in order to minimize trace parasitics. If the trace inductance

maximum voltage rating and damage the device. This situation can be mitigated by additional input capacitors to

dampen and keep the ringing below the device absolute maximum ratings.

A combination of multiple output capacitors boosts the high-frequency PSRR. The combination of one 0805-

sized, 47-µF ceramic capacitor in parallel with two 0805-sized, 10-µF ceramic capacitors with a sufficient voltage

rating, in conjunction with the PSRR boost circuit, optimizes PSRR for the frequency range of 400 kHz to

700 kHz, a typical range for dc/dc supply switching frequency. This 47-µF || 10-µF || 10-µF capacitor combination

also makes certain that at high input voltage and high output voltage configurations, the minimum effective

capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a voltage derating of approximately 60% to

80% at 5.0 V, so the addition of the two 10-µF capacitors makes sure that the capacitance is at or above 22 µF.