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XRT75VL00D 数据表(PDF) 21 Page - Exar Corporation |
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XRT75VL00D 数据表(HTML) 21 Page - Exar Corporation |
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21 / 92 page ![]() XRT75VL00D REV. 1.0.3 E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 16 2.0 TIMING CHARACTERISTICS FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75VL00D (DUAL-RAIL DATA) FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING SYMBOL PARAMETER MIN TYP MAX UNITS TxClk Duty Cycle E3 DS3 STS-1 30 50 34.368 44.736 51.84 70 % MHz MHz MHz tRTX TxClk Rise Time (10% to 90%) 4 ns tFTX TxClk Fall Time (10% to 90%) 4 ns tTSU TPData/TNData to TxClk falling set up time 3 ns tTHO TPData/TNData to TxClk falling hold time 3 ns tTDY TTIP/TRing to TxClk rising propagation delay time 8 ns Terminal Equipment (E3/DS3 or STS-1 Framer) Exar E3/DS3/STS-1 LIU Transmit Logic Block TxPOS TxNEG TxLineClk TPData TNData TxClk TPData or TN Data TTIP or TRing TxC lk t TSU t THO t RTX t FTX t TDY |
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