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DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
7
Version: DM9601-DS-F01
June 22, 2002
5.4 Clock Interface
21
X2_25M
I/O
Crystal 25MHz Out
22
X1_25M
I/O
Crystal 25MHz In
59
CLK20MO
I/O
20Mhz Clock Output
5.5 LED Interface
60
SPEED100#
O
Speed LED
It’s low output indicates that the internal PHY is operated in 100M speed,
or it is floating for the 10M mode of the internal PHY.
61
DUP#
O
Full-duplex LED
In LED mode 1, It’s low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the
internal PHY.
In LED mode 0, It’s low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY.
62
LINK&ACT#
O
Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY.
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only.
5.6 10/100 PHY/Fiber
24
SD
I
Fiber-optic Signal Detect
PECL signal indicates whether or not the fiber-optic receives pair is
receiving valid levels.
25
AGND
Bandgap Ground.
26
BGRES
I/O
Bandgap Pin.
27
AVDD
Bandgap and Guard Ring Power
28
AVDD
RX Power
29
RX+
I
TP RX Input
30
RX-
I
TP RX Input
31
AGND
RX Ground
32
AGND
TX Ground
33
TXO+
O
TP TX Output
34
TXO-
O
TP TX Output
35
AVDD
TX Power
5.7 Miscellaneous
16
MII MODE
I
Tie to DVDD if connects with Ethernet’s PHY through External MII.
Otherwise tie it to ground.
48
TEST5
I
It Must be Ground
68,69,70,
71,82,83,
84
GPIO0~6
I/O
General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode with output data high at default to power
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