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CS5541 数据表(PDF) 11 Page - Cirrus Logic |
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CS5541 数据表(HTML) 11 Page - Cirrus Logic |
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11 / 26 page ![]() CS5541 DS500PP1 11 2.2 Voltage Reference Input The differential voltage between VREF+ and VREF- sets the nominal full scale input range of the converter. For a single-ended reference voltage, the reference output is connected to the VREF+ pin of the CS5541 and the ground reference is connect- ed to the VREF- pin. Note that the differential ref- erence voltage can be from 0.1 V to ((VA+)- (VA-)). The noise-free resolution of a single sam- ple from the ADC is directly proportional to the voltage reference as depicted in Figures 6 and 7. Note: When a lower reference voltage is used, the resulting code widths are smaller. Since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier. 2.2.1 Voltage Reference Input Model Figure 8 illustrates the input models for the VREF pins. It includes a coarse/fine charge buffer which reduces the dynamic current demand on the exter- nal reference. The reference’s buffer is designed to accommodate rail-to-rail (common-mode plus sig- nal) input voltages. Typical CVF (sampling) cur- rent is about 20 nA (MCLK = 32.768 kHz; see Figure 8). 14 15 16 17 18 19 20 00.511.5 2 2.5 3 VREF (V) Figure 6. Typical Noise-Free Resolution vs. Voltage Reference One-Time Cal, 4 Cycle Settling, 50/60 Hz Reject Noise-Free Res. = log2 (Bipolar Span/6.6*RMS Noise) 13 14 15 16 17 18 19 0 0.5 1 1.5 2 2.5 3 VREF (V) Figure 7. Typical Noise-Free Resolution vs. Voltage Reference Continuous Cal, 1Cycle Settling, 50/60 Hz Reject Noise-Free Res. = log2 (Bipolar Span/6.6*RMS Noise) VREF C = 12 pF f = 2*MCLK = 65.536 kHz φ Coarse 2 φ Fine 1 i n = CV osf V os ≤ 25mV Figure 8. Input model for VREF+ and VREF- pins. |
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