CS7620 datasheet(49/70 Pages) CIRRUS

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CS7620

DS301PP2

4.31

Horizontal Timing Control - H2

Default = 7Ah; Read/Write (address 2Ah)

Bit Number

765432

Bit Name

Reserved

h2d

h2f_reg2

h2f_reg1

h2g_reg0

h2g_reg2

h2g_reg1

h2g_reg0

Default

1111010

Bit

Mnemonic

Function

Reserved

6h2d

H2 Default Setting: During the vertical shift time, the horizontal clocks are

held in one state. This bit controls whether H2 is held high or low during this

time.

A “0” indicates that the signal state is low, a “1” indicates that the signal state

is high.

h2f_reg2

H2 Falling Edge: The phase of the falling edge of H2 can be programmed

through this register. The falling edge of H2 corresponds to the rising edge of

the internally selected clock. The phases of these clocks are shown in Figure

19, with the complemented clocks being the inverse of these.

0 = t0

1 = t1

2 = t2

3 = t3

4 = t4

5 = t5

6 = t6

7 = t7

(See Figure 19)

h2f_reg1

h2g_reg0

h2g_reg2

H2 Rising Edge: The phase of the rising edge of H2 can be programmed

through this register. The rising edge of H2 corresponds to the rising edge of

the internally selected clock. The phases of these clocks are shown in Figure

19, with the complemented clocks being the inverse of these.

0 = t0

1 = t1

2 = t2

3 = t3

4 = t4

5 = t5

6 = t6

7 = t7

(See Figure 19)

h2g_reg1

h2g_reg0

CS7620 数据表(PDF) 49 Page - Cirrus Logic

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CS7620 数据表(PDF) 49 Page - Cirrus Logic

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