CS8427-CSZ datasheet(57/59 Pages) CIRRUS

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CS8427

DS477F3

19.3.3

Locking to the ILRCK Input

CS8427 parts that are configured to lock to the IL-

RCK input should use the external PLL component

values listed in Table 8. Note that parts that need

to lock to both ILRCK and RXP/RXN should use

these values. Values listed for the 32 to 96 kHz Fs

range will have the highest corner frequency jitter

attenuation curve, take the shortest time to lock,

and offer the best output jitter performance.

19.3.4

Jitter Tolerance

Shown in Figure 32 is the Receiver Jitter Tolerance

template as illustrated in the AES3 and IEC60958-

4 specification. CS8427 parts used with the appro-

priate external PLL component values (as noted in

Table 7) have been tested to pass this template.

Revision

Fs Range

(kHz)

RFILT (kΩ)CFILT (µF) CRIP (nF) PLL Lock Time (ms)

8 to 96

1.3

2.7

120

32-96

5.1

0.15

3.9

A1/A2

8 to 96

0.3

1.0

100

120

A1/A2

32-96

0.6

0.22

Table 8. Locking to the ILRCK Input

Figure 32. Jitter Tolerance Template

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