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CS44600 数据表(PDF) 3 Page - Cirrus Logic |
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CS44600 数据表(HTML) 3 Page - Cirrus Logic |
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3 / 78 page ![]() DS633PP1 3 CS44600 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8 SPECIFIED OPERATING CONDITIONS ...................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ................................................................................................. 8 DC ELECTRICAL CHARACTERISTICS ........................................................................................ 9 DIGITAL INTERFACE CHARACTERISTICS ................................................................................. 9 PWM OUTPUT PERFORMANCE CHARACTERISTICS ............................................................. 10 PWM FILTER CHARACTERISTICS ............................................................................................ 11 SWITCHING CHARACTERISTICS - XTI ..................................................................................... 11 SWITCHING CHARACTERISTICS - SYS_CLK .......................................................................... 12 SWITCHING CHARACTERISTICS - PWMOUTA1-B3 ................................................................ 12 SWITCHING CHARACTERISTICS - PS_SYNC .......................................................................... 12 SWITCHING CHARACTERISTICS - DAI INTERFACE ............................................................... 13 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ...................................... 14 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ..................................... 15 2. PIN DESCRIPTIONS .............................................................................................................. 16 2.1 I/O Pin Characteristics ..................................................................................................... 19 3. TYPICAL CONNECTION DIAGRAMS ................................................................................... 20 4. APPLICATIONS ..................................................................................................................... 22 4.1 Overview .......................................................................................................................... 22 4.2 Feature Set Summary ..................................................................................................... 22 4.3 Clock Generation ............................................................................................................. 23 4.3.1 FsIn Domain Clocking ......................................................................................... 24 4.3.2 FsOut Domain Clocking ...................................................................................... 24 4.4 FsIn Clock Domain Modules ............................................................................................ 26 4.4.1 Digital Audio Input Port ....................................................................................... 26 4.4.2 Auto Rate Detect ................................................................................................. 30 4.4.3 De-Emphasis ...................................................................................................... 30 4.5 FsOut Clock Domain Modules ......................................................................................... 31 4.5.1 Sample Rate Converter ...................................................................................... 31 4.5.2 Load Compensation Filter ................................................................................... 31 4.5.3 Digital Volume and Mute Control ........................................................................ 31 4.5.4 Peak Detect / Limiter ........................................................................................... 32 4.5.5 PWM Engines ..................................................................................................... 32 4.5.6 Interpolation Filter ............................................................................................... 33 4.5.7 Quantizer ............................................................................................................ 33 4.5.8 Modulator ............................................................................................................ 33 4.5.9 PWM Outputs ...................................................................................................... 33 4.5.10 Power Supply Rejection (PSR) Real-Time Feedback ....................................... 34 4.6 Control Port Description and Timing ................................................................................ 35 4.6.1 SPI Mode ............................................................................................................ 35 4.6.2 I²C Mode ............................................................................................................. 36 4.6.3 GPIOs ................................................................................................................. 37 4.6.4 Host Interrupt ...................................................................................................... 37 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ......................................................... 38 5.1 Reset and Power-Up ....................................................................................................... 41 5.1.1 PWM PopGuard® Transient Control ................................................................... 41 5.1.2 Recommended Power-Up Sequence ................................................................. 41 5.1.3 Recommended PSR Calibration Sequence ....................................................... 42 5.1.4 Recommended Power-Down Sequence ............................................................. 43 6. REGISTER QUICK REFERENCE .......................................................................................... 44 7. REGISTER DESCRIPTION .................................................................................................... 48 7.1 Memory Address Pointer (MAP) ...................................................................................... 48 |
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