Revision 1.6
-13-
02/28/2000
TXOE: Endpoint 0 FIFO data ready bit
1: Endpoint 0 FIFO data are ready to be transmitted. Data will be transmitted when a valid IN token is
received. This bit is automatically cleared by hardware after the transaction complete (ACK is received).
0: Endpoint 0 FIFO data are not ready to be transmitted and respond with a NAK to a valid IN transaction.
TXCNT[3:0]: Number of bytes to be sent by endpoint 0 when IN token is received
Value on POR: “0 0 0 0 0 0 0 0”
TXCTL123(Address 15h, Endpoint 1/2/3 transmit control register)
R/W
R/W
R/W
R/W
R/W
R/W
TXSEQ
TXOE
TXCNT3
TXCNT2
TXCNT1
TXCNT0
TXSEQ: Endpoint 1/2/3 transmitting sequence bit
1: Transmitting data use DATA1 as PID
0: Transmitting data use DATA0 as PID
TXOE: Endpoint 1/2/3 FIFO data ready bit
1: Endpoint 1/2/3 FIFO data are ready to be transmitted. Data will be transmitted when a valid IN token is
received. This bit is automatically cleared by hardware after the transaction complete (ACK is received).
0: Endpoint 1/2/3 FIFO data are not ready to be transmitted and respond with a NAK to a valid IN transaction.
TXCNT[3:0]: Number of bytes to be sent by endpoint 0 when IN token is received
Value on POR: “0 0 0 0 0 0 0 0”
FFDAT0 (Address 16h, Endpoint 0 FIFO port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7
FFDAT6
FFDAT5
FFDAT4
FFDAT3
FFDAT2
FFDAT1
FFDAT0
Endpoint 0 FIFO data port
Endpoint 0 FIFO is a 8 bytes FIFO. Firmware can read/write this port 8 times to get/put the FIFO data.
Value on POR: “X X X X X X X X”
FFDAT1/2/3 (Address 17h, Endpoint 1/2/3 FIFO port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7
FFDAT6
FFDAT5
FFDAT4
FFDAT3
FFDAT2
FFDAT1
FFDAT0
Endpoint 1/2/3 FIFO data port
Endpoint 1 FIFO is 8 bytes FIFO. Firmware can read this port 8 times to get the FIFO data.
Endpoint 2 FIFO is 6 bytes FIFO. Firmware can read this port 6 times to get the FIFO data.
Endpoint 3 is 2 bytes FIFO only. Firmware can read this port 2 times to get the FIFO data.
Before read this register, firmware should selects endpoint via EPSEL register (address 1Dh).
Value on POR: “X X X X X X X X”
DRVSEL (Address 18h, Key matrix drive pin control register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INVDRV
DRVOE
DRV4
DRV3
DRV2
DRV1
DRV0
INVDRV: Inverse drive signal. This function can be used to detected ghost keys.
1: Drive all DRV1-18 to low except the selected pin when DRVOE is set
0: Drive the selected pin to low only when DRVOE is set
DRVOE: DRV1-18 output enable
1: Enable DRV1-18 pins to drive key matrix
0: Disable DRV1-18 pins and not to drive key matrix
DRV[4:0]: Select DRV1 to DRV18 port to drive low if DRVOE is set.
5’h00 selects DRV1
5’h01 selects DRV2
5’h0f selects DRV16
5’h10 selects DRV17
5’h11 selects DRV18
5’h12 ~ 5’h1f are invalid.
Value on POR: “0 0 0 0 0 0 0 0”
SENSE (Address 19h, Key matrix sense resister)
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