STM32MP153D datasheet(22/254 Pages) STMICROELECTRONICS

22 / 254 page

Functional overview

STM32MP153A/D

22/254

DS12502 Rev 3

This routing flexibility and the support for virtualization of interrupts into the operating

system, provides one of the key features required to enhance the capabilities of a solution

utilizing a hypervisor.

3.2

Arm® Cortex®-M4 with FPU

The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional

code-efficiency, delivering the high-performance expected from an Arm core in the memory

size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

Note:

Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.

Memory protection unit (MPU)

The memory protection unit (MPU) manages the Cortex®-M4 access rights and the

attributes of the system resources. It has to be programmed and enabled before use. Its

main purposes are to prevent an untrusted user program to accidentally corrupt data used

by the OS and/or by a privileged task, but also to protect data processes or read-protect

memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It

allows the definition of up to 16 protected regions that can in turn be divided into up to 8

independent subregions, where region address, size, and attributes can be configured. The

protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is

generated.

STM32MP153D 数据表(PDF) 22 Page - STMicroelectronics