MC74AC174, MC74ACT174

http://onsemi.com

2

Figure 2. Logic Symbol

CP

MR

FUNCTIONAL DESCRIPTION

The

MC74AC174/74ACT174

consists

of

six

edge−triggered D flip−flops with individual D inputs and Q

outputs. The Clock (CP) and Master Reset (MR) are

common to all flip−flops. Each D input’s state is transferred

to the corresponding flip−flop’s output following the

LOW−to−HIGHClock (CP) transition. A LOW input to the

Master Reset (MR) will force all outputs LOW independent

of Clock or Data inputs. The MC74AC174/ 74ACT174 is

useful for applications where the true output only is required

and the Clock and Master Reset are common to all storage

elements.

Figure 3. Logic Diagram

CP

MR

Q

CD

NOTE: This diagram is provided only for the understanding of logic

operations and should not be used to estimate propagation

delays.

CP

D

Q

CD

CP

D

Q

CD

CP

D

Q

CD

CP

D

Q

CD

CP

D

Q

CD

CP

D

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

−0.5 to +7.0

V

DC Input Voltage (Referenced to GND)

V

DC Output Voltage (Referenced to GND)

V

DC Input Current, per Pin

±20

mA

DC Output Sink/Source Current, per Pin

±50

mA

±50

mA

Storage Temperature

−65 to +150

°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-

mended Operating Conditions.