 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AM6546 数据表(PDF) 96 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM6546 数据表(HTML) 96 Page - Texas Instruments |
|
|
96 / 277 page  96 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2019, Texas Instruments Incorporated (1) When OSC1 is being used with an external crystal, this signal is unavailable. The output functionality must be disabled. 4.3.22 SERDES 4.3.22.1 MAIN Domain Table 4-55. SERDES0 Signal Descriptions(1) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES0_REFCLKN SERDES Clock Input (negative) I AG5 SERDES0_REFCLKP SERDES Clock Input (positive) I AG6 SERDES0_REFRES SERDES Reference Resistor(2) A AC9 SERDES0_RXN SERDES Differential Receive Data (negative) I AH3 SERDES0_RXP SERDES Differential Receive Data (positive) I AG2 SERDES0_TXN SERDES Differential Transmit Data (negative) O AH4 SERDES0_TXP SERDES Differential Transmit Data (positive) O AG3 (1) The functionality of these pins is controlled by CTRLMMR_SERDES0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = USB3, 0x1 = PCIe0 Lane0, 0x2 = ICSS2 SGMII Lane0. (2) The required resistor value is 3k Ω ±1%. Table 4-56. SERDES1 Signal Descriptions(1) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES1_REFCLKN SERDES Clock Input (negative) I AH6 SERDES1_REFCLKP SERDES Clock Input (positive) I AH7 SERDES1_REFRES SERDES Reference Resistor(2) A AC14 SERDES1_RXN SERDES Differential Receive Data (negative) I AG9 SERDES1_RXP SERDES Differential Receive Data (positive) I AH10 SERDES1_TXN SERDES Differential Transmit Data (negative) O AH9 SERDES1_TXP SERDES Differential Transmit Data (positive) O AG8 (1) The functionality of these pins is controlled by CTRLMMR_SERDES1_CTRL[1:0] LANE_FUNC_SEL. 0x0 = PCIe1 Lane0, 0x1 = PCIe0 Lane1, 0x2 = ICSS2 SGMII Lane1. (2) The required resistor value is 3k Ω ±1%. 4.3.23 UART 4.3.23.1 MAIN Domain Table 4-57. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART0_CTSn UART Clear to Send (active low) I AG11 UART0_DCDn UART Data Carrier Detect (active low) I D25 UART0_DSRn UART Data Set Ready (active low) I B26 UART0_DTRn UART Data Terminal Ready (active low) O A24 UART0_RIN UART Ring Indicator I E24 UART0_RTSn UART Request to Send (active low) O AD11 UART0_RXD UART Receive Data I AF11 UART0_TXD UART Transmit Data O AE11 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
