PCF2129 datasheet(47/86 Pages) PHILIPS

47 / 86 page

PCF2129

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Product data sheet

Rev. 7 — 19 December 2014

47 of 86

NXP Semiconductors

PCF2129

Accurate RTC with integrated quartz crystal for industrial applications

The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock

and generates a pulse of 1⁄64 seconds in duration.

8.12.2 INT pulse shortening

If the MSF flag (register Control_2) is cleared before the end of the INT pulse, then the

INT pulse is shortened. This allows the source of a system interrupt to be cleared

immediately when it is serviced, that is, the system does not have to wait for the

completion of the pulse before continuing; see Figure 24. Instructions for clearing the bit

MSF can be found in Section 8.10.5.

8.12.3 Watchdog timer interrupts

The generation of interrupts from the watchdog timer is controlled using the WD_CD bit

(register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows

the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is

possible for watchdog timer interrupts.

The interrupt is cleared when the flag WDTF is reset. WDTF is a read-only bit and cannot

be cleared by command. Instructions for clearing it can be found in Section 8.10.5.

8.12.4 Alarm interrupts

Generation of interrupts from the alarm function is controlled by the bit AIE (register

Control_2). If AIE is enabled, the INT pin follows the status of bit AF (register Control_2).

Clearing AF immediately clears INT. No pulse generation is possible for alarm interrupts.

(1) Indicates normal duration of INT pulse.

The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is, when

TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0.

Fig 24. Example of shortening the INT pulse by clearing the MSF flag

PCF2129 数据表(PDF) 47 Page - NXP Semiconductors