FSYNC

BCLK

SDOUT

7

PCM1840

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SBAS989 – APRIL 2019

Product Folder Links: PCM1840

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(1)

The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is

latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

6.6 Timing Requirements: TDM, I

MIN

NOM

MAX

UNIT

BCLK period

40

ns

18

ns

18

ns

FSYNC setup time

8

ns

FSYNC hold time

8

ns

BCLK rise time

10% - 90% rise time

10

ns

BCLK fall time

90% - 10% fall time

10

ns

(1)

The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on

the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

6.7 Switching Characteristics: TDM, I

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BCLK to SDOUT delay

50% of BCLK to 50% of SDOUT

18

ns

FSYNC to SDOUT delay in TDM

or LJ mode (for MSB data with

TX_OFFSET = 0)

50% of FSYNC to 50% of

SDOUT

18

ns

BCLK output clock frequency:

24.576

MHz

BCLK high pulse duration:

master mode

14

ns

BCLK low pulse duration: master

mode

14

ns

BCLK to FSYNC delay: master

mode

50% of BCLK to 50% of FSYNC

18

ns

BCLK rise time: master mode

10% - 90% rise time

8

ns

BCLK fall time: master mode

90% - 10% fall time

8

ns