MAS2901CS datasheet(5/13 Pages) ZARLINK

5 / 13 page

MA2901

In the shift up mode, the RAM3 buffer is enabled and the

RAM0 multiplexer input is enabled. Likewise, in the shift down

mode, the RAM0 buffer and RAM3 input are enabled. In the no-

shift mode, both buffers are in the high-impedance state and

the multiplexer inputs are not selected. The shifter is controlled

from the I6, I7 and I8 microinstruction inputs as defined in Figure

Similarly, the Q register is driven from a 3-input

multiplexer. In the non-shift mode, the multiplexer enters the

ALU data into the Q register. In either the shift-up or shift-down

mode, the multiplexer selects the Q register data appropriately

shifted up or down. The Q shifter also has two ports; one is

labeled Q0 and the other is Q3. The operation of these two

ports is similar to the RAM shifter and is also controlled from I6,

I7 and I8 as shown in Figure 4.

The clock input shown in Figure 1 controls the RAM, the Q

resister and the A and B data latches. When enabled, data is

clocked into the Q register on the LOW-to-HlGH transition of

the clock. When the clock input is HIGH, the A and B latches

are open and will pass whatever data is present at the RAM

outputs. When the clock input is LOW, the latches are closed

and will retain the last data entered. If the RAM-EN is enabled

new data will be written into the RAM file (word) defined by the

B address field when the clock input is LOW.

SOURCE OPERANDS & ALU FUNCTION

Any one of eight source operand pairs can be selected by

instruction inputs lo, l1 and I2 for use by the ALU; instruction

inputs I3, I4, and I5 then control function selection for the ALU -

five logic and three arithmetic functions. In the arithmetic

mode, the carry input (Cn) also affects the ALU functions; the

carry input has no effect on the ‘F’ result in the logic mode.

These control parameters (I6 - l0 and Cn) are summarised in

Figure 5 to completely define the ALU/source operand

functions.

The ALU functions can also be examined on a task basis:

that is, add, subtract, AND, OR, and so on. Again, in the

arithmetic mode, the carry input still affects the result, whereas

in the logic mode it will not. Figures 6 and 7, respectively,

define the various logic and arithmetic functions of the ALU;

both carry states (Cn = 0 / Cn = 1) are defined in the function

matrices.

X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a TRI-STATE output which is in the high-impedance state.

B = Register addressed by 8 inputs. Up is towards MSB, Down is towards LSB.

Figure 4: ALU Destination Control

I 2,1,0Octal

Octal

I 5,4,3

ALU Source

/ALU

Function

A,Q

A,B

0,Q

0,B

0,A

D,A

D,Q

D,0

Cn=L

R plus S

Cn=H

A+Q

A+Q+1

A+B

A+B+1

Q +1

B + 1

A + 1

D + A

D + A + 1

D + Q

D + Q + 1

D + 1

Cn=L

S minus R

Cn=H

Q-A-1

Q-A

B-A-1

B-A

Q -1

B - 1

A - 1

A - D1

A - D

Q - D - 1

Q - D

-D - 1

- D

Cn=L

R minus S

Cn=H

A-Q-1

A-Q

A-B-1

A-B

-Q-1

- Q

- B - 1

- B

- A - 1

- A

D - A -1

D - A

D - Q - 1

D - Q

D - 1

R or S

A V Q

A V B

D V A

D V Q

R and S

Λ Q

Λ B

Λ A

Λ Q

RN and S

Λ Q

Λ B

Λ A

Λ Q

R EX-OR S

∇ Q

∇ B

∇ A

∇ Q

R EX NOR S

∇ QN

∇ BN

∇ AN

∇ QN

+ = plus; - = minus; V = OR; Λ = AND; ∇ = EX-OR

Figure 5: Source Operand and ALU Function Matrix

Microcode

RAM Function

Q-Reg Function

RAM Shifter

Q Shifter

Octal

Code

Shift

Load

Shift

Load

Output

RAM0

RAM3

None

→ Q

None

→ B

None

→ B

None

Down

F/2

→ B

Q/2

→ Q

IN3

Down

F/2

→ B

None

IN3

→ B

→ Q

IN0

IN3

→ B

None

IN0

MAS2901CS 数据表(PDF) 5 Page - Zarlink Semiconductor Inc

MAS2901CS 数据表(HTML) 5 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

数据表下载

链接网址

MAS2901CS 数据表(PDF) 5 Page - Zarlink Semiconductor Inc

MAS2901CS 数据表(HTML) 5 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

数据表 下载

链接网址

数据表下载