M58LT128GS datasheet(13/98 Pages) STMICROELECTRONICS

13 / 98 page

M58LT128GST, M58LT128GSB

2 Signal descriptions

13/98

Signal descriptions

See Figure 1: Logic Diagram and Table 1: Signal Names, for a brief overview of the signals

connected to this device.

2.1

Address Inputs (A0-A22)

The Address Inputs select the cells in the memory array to access during Bus Read operations.

During Bus Write operations they control the commands sent to the Command Interface of the

Program/Erase Controller.

2.2

Data Input/Output (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

2.3

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and sense

amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When

Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power

consumption is reduced to the stand-by level.

2.4

Output Enable (G)

The Output Enable input controls data outputs during the Bus Read operation of the memory.

2.5

Write Enable (W)

The Write Enable input controls the Bus Write operation of the memory’s Command Interface.

The data and address inputs are latched on the rising edge of Chip Enable or Write Enable

whichever occurs first.

2.6

Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is

in reset mode: the outputs are high impedance and the current consumption is reduced to the

Reset Supply Current IDD2. Refer to Table 20: DC Characteristics - Currents, for the value of

IDD2. After Reset all blocks are in the Protected state and the Configuration Register is reset.

When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters

asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required

to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to

VRPH (refer to Table 21: DC Characteristics - Voltages).

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