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CDP1824CD3 数据表(PDF) 3 Page - Intersil Corporation

部件名 CDP1824CD3
功能描述  High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory
PDF  5 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

CDP1824CD3 数据表(HTML) 3 Page - Intersil Corporation

  CDP1824CD3 Datasheet HTML 1Page - Intersil Corporation CDP1824CD3 Datasheet HTML 2Page - Intersil Corporation CDP1824CD3 Datasheet HTML 3Page - Intersil Corporation CDP1824CD3 Datasheet HTML 4Page - Intersil Corporation CDP1824CD3 Datasheet HTML 5Page - Intersil Corporation  
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Read Cycle Dynamic Electrical Specifications
Input tR, tF ≤ 15ns, CL = 50pF
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
-55oC, +25oC+125oC
VDD
(V)
MIN
MAX
MIN
MAX
Access Time From Address Change
tAA
5
-
610
-
825
ns
10
-
320
-
375
ns
Access Time From Chip Select
tDOA
5
-
610
-
825
ns
10
-
320
-
375
ns
Output Active From MRD
tAM
5
-
610
-
825
ns
10
-
320
-
375
ns
NOTE:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAM
tAM
(NOTE 1)
tAA
tDOA
(NOTE 1)
HIGH IMPEDANCE
MRD
MA
CS
DATA OUT
CDP1824/3, CDP1824C/3



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