5

Data-In After Clock Fall Hold Time

5

150

-

170

-

ns

10

70

-

100

-

ns

Propagation Delay Times:

Clear to SR

5

-

200

-

340

ns

10

-

110

-

170

ns

Clock to SR

5

-

175

-

220

ns

10

-

110

-

130

ns

Deselect to SR

5

-

175

-

240

ns

10

-

110

-

120

ns

NOTE:

1. Time required by a device to allow for the indicated function.

NOTE:

1. CS1

MODE = 0 TRUTH TABLE

SERVICE REQUEST

TRUTH TABLE

CLOCK

CS1

DATA OUT EQUALS

X

0

X

High Impedance

Clock =

CS1 or CS2 =

or CLEAR = 0

010

0

011

Data Latch

1

1

X

Data In

SR = 0

SR = 1

NOTE:

1. CS1

FIGURE 3. MODE = 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES

Dynamic Electrical Specifications

PARAMETER

SYMBOL

VOLTS

LIMITS (NOTE 1)

UNITS

(NOTE 1)

MIN

MAX

(NOTE 1)

MIN

MAX

CS1

• CS2

CLOCK

DATA IN

DATA BUS

SR

CLEAR

HIGH

IMPEDANCE

(NOTE 1)

CDP1852/3, CDP1852C/3