AM79C930 datasheet(16/161 Pages) AMD

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Am79C930

PRELIMINARY

PCMCIA PIN FUNCTION SUMMARY

PCMCIA Pin Summary

No. of

Pins

Pin Name

Pin Function

Pin Style

A14–A0

PCMCIA address bus lines

D7–D0

PCMCIA data bus lines

TS2

RESET

PCMCIA bus RESET line

CE1

Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write

accesses

Output Enable—used to enable the output drivers of the Am79C930 device for

PCMCIA Read accesses

Write Enable—used to indicate that the current PCMCIA cycle is a write access

REG

REG—used to indicate that the current PCMCIA cycle is to the Attribute

Memory space of the Am79C930 device

INPACK

Input Acknowledge—used to indicate that the Am79C930 device will respond

to the current I/O read cycle

TS1

WAIT

Wait—used to delay the termination of the current PCMCIA cycle

TS2

IORD

I/O Read—this signal is asserted by the PCMCIA host system whenever an

I/O read operation occurs

IOWR

I/O Write—this signal is asserted by the PCMCIA host system whenever an

I/O write operation occurs

IREQ

Interrupt Request—this line is asserted when the Am79C930 device needs

servicing from the software

PTS3

STSCHG

Status Change—PCMCIA output used only for WAKEUP signaling

PTS1

PCMCIA

PCMCIA mode—selects PCMCIA or ISA Plug and Play mode

PWRDWN

Powerdown—indicates that device is in the power down mode

TP1

MA16–0

Memory Address Bus—these lines are used to address locations in the Flash

device, the SRAM device, and an extra peripheral device that are contained

within an Am79C930-based design

TP1

MD7–0

Memory Data Bus—these lines are used to write and read data to/from Flash,

SRAM, and/or an extra peripheral device within an Am79C930-based design

TS1

FCE

Flash Chip Enable—this signal becomes asserted when the Flash device has

been addressed by either the 80188 core of the Am79C930 device or by the

software through the PCMCIA interface

TP1

SCE

SRAM Chip Enable—this signal becomes asserted when the SRAM device

has been addressed by either the 80188 core of the Am79C930 device or by

the software through the PCMCIA interface

TP1

XCE

eXtra Chip Enable—this signal becomes asserted when the extra peripheral

device has been addressed by the 80188 core of the Am79C930 device (XCE

is not accessible through the system interface)

TP1

MOE

Memory Output Enable—this signal becomes asserted during reads of devices

located on the memory interface bus

TP1

MWE

Memory Write Enable—this signal becomes asserted during writes to devices

located on the memory interface bus

TP1

TCK

Test Clock—this is the clock signal for IEEE 1149.1 testing

TDI

Test Data In—this is the data input signal for IEEE 1149.1 testing

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