XRT7250 datasheet(21/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

XIX

Table 63:Listing and Description of the Pin Associated with the Receive Overhead Data Output Interface Block

(For Method 1) .............................................................................................................................................. 311

Table 64:The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame was

last sampled "High”) to the E3 Overhead Bit, that is being output via the RxOH output pin ......................... 311

Table 65:Listing and Description of the Pin Associated with the Receive Overhead Data Output Interface Block

(Method 2) ..................................................................................................................................................... 313

Table 66:The Relationship between the Number of RxOHEnable output pulses (since RxOHFrame was last

sampled "High") to the E3 Overhead Bit, that is being output via the RxOH output pin ............................... 315

Table 67:Listing and Description of the pin associated with the Receive Payload Data Output Interface block ..

317

Table 68:Definition of the Trail Trace Buffer Bytes, within The E3, ITU-T G.832 Framing Format ............... 333

Table 69:A Listing of the Various Payload Type Values and their corresponding Meaning .......................... 335

Table 70:Listing and Description of the pins associated with the Transmit Payload Data Input Interface .... 338

Table 71:A Listing of the Overhead bits within the E3 frame, and their potential sources, within the XRT7250 IC

354

Table 72:Description of Method 1 Transmit Overhead Input Interface Signals ............................................. 356

Table 73:The Relationship between the Number of Rising Clock Edges in TxOHClk, (since "TxOHFrame" was

last sampled "High") to the E3 Overhead Bit, that is being processed ......................................................... 358

Table 74:Description of Method 1 Transmit Overhead Input Interface Signals ............................................. 361

Table 75:The Relationship between the Number of TxOHEnable pulses (since the last occurrence of the TxO-

HFrame pulse) to the E3 Overhead Bit, that is being processed by the XRT7250 ....................................... 363

Table 76:The LAPD Message Type and the Corresponding value of the First Byte, within the Information Pay-

load ............................................................................................................................................................... 366

Table 77:Relationship between TxLAPD Msg Length and the LAPD Message Size .................................... 367

Table 78:The Relationship between the contents of Bit 2 (Tx AIS Enable) within the Tx E3 Configuration Regis-

ter, and the resulting Transmit E3 Framer Block's Action ............................................................................. 375

Table 79:The Relationship between the contents of Bit 1 (Tx LOS) within the Tx E3 Configuration Register, and

the resulting Transmit E3 Framer Block's Action .......................................................................................... 375

Table 80:The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Control Register

and the Transmit E3 Framer Line Interface Output Mode ............................................................................ 379

Table 81:The Relationship between Bit 4 (AMI/HDB3*) within the I/O Control Register and the Bipolar Line Code

that is output by the Transmit E3 LIU Interface Block ................................................................................... 381

Table 82:The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control Register and the

TxLineClk clock edge that TxPOS and TxNEG are updated on ................................................................... 381

Table 83:The Relationship between the contents of Bit 2 (TxLineClk Inv) within the I/O Control Register and the

TxLineClk clock edge that TxPOS and TxNEG are updated on ................................................................... 386

Table 84:The Relationship between the contents of Bit 1 (RxLineClk Inv) of the I/O Control Register, and the

sampling edge of the RxLineClk signal ......................................................................................................... 389

Table 85:The Relationship between the Logic State of the RxOOF and RxLOF output pins, and the Framing

State of the Receive E3 Framer block .......................................................................................................... 397

Table 86:The Relationship between the Contents of RxLAPDType[1:0] bit-fields and the PMDL Message Type/

Size ............................................................................................................................................................... 409

Table 87:Listing and Description of the Pin Associated with the Receive Overhead Data Output Interface Block

414

Table 88:The Relationship between the Number of Rising Clock Edges in RxOHClk, (since RxOHFrame was

last sampled "High") to the E3 Overhead Bit, that is being output via the RxOH output pin ......................... 414

Table 89:Listing and Description of the Pin Associated with the Receive Overhead Data Output Interface Block

(Method 2) ..................................................................................................................................................... 418

Table 90:The Relationship between the Number of RxOHEnable output pulses (since RxOHFrame was last

sampled "High") to the E3 Overhead Bit, that is being output via the RxOH output pin ............................... 420

Table 91:Listing and Description of the pin associated with the Receive Payload Data Output Interface block ..

424

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