AUIPS2041(L)(R)

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6

Figure 1

– Timing diagram

All curves are typical values. Operating in the shaded area is not recommended.

Vds

Ids

Vin

IN

D

S

R

L

0V

5V

14V

+

-

V load

Rem : During active clamp,

Vload is negative

Tj

Isd

Tsd

165°C

Ids

Vin

Ishutdown

Tshutdown

t<T reset

t>T reset

Vdiag

fault

normal

Vds

Ids

Vin

Tr-in

80%

20%

80%

20%

Td on

Tr

Td off

Tf

Figure 2

– IN rise time & switching definitions

Vds

Ids

Vin

Vcc

Vds clamp

T clamp

See Application Notes to evaluate power dissipation

Figure 3

– Active clamp waveforms

Figure 4

– Active clamp test circuit