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M054LDN 数据表(PDF) 49 Page - Nuvoton Technology Corporation

部件名 M054LDN
功能描述  ARM짰 Cortex짰-M0 32-bit Microcontroller
PDF  86 Pages
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制造商  NUVOTON [Nuvoton Technology Corporation]
网页  http://www.nuvoton.com
标志 NUVOTON - Nuvoton Technology Corporation

M054LDN 数据表(HTML) 49 Page - Nuvoton Technology Corporation

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M051 DN/DE
Oct. 05, 2015
Page 49 of 86
Rev 1.03
I
2C Serial Interface Controller (I2C)
6.12
6.12.1 Overview
I
2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I
2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. There are two sets of I
2C which supports Power-down wake-up function.
6.12.2 Features
The I
2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I
2C bus include:
Supports up to two I
2C ports
Master/Slave mode
Bidirectional data transfer between master and slave
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Built-in a 14-bit time-out counter requesting the I
2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down Wake-up function



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