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TLE2071IP 数据表(PDF) 67 Page - Texas Instruments

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部件名 TLE2071IP
功能描述  EXCALIBUR LOW-NOISE HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS
PDF  81 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TLE2071IP 数据表(HTML) 67 Page - Texas Instruments

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TLE207x, TLE207xA
EXCALIBUR LOW NOISE HIGHSPEED
JFET INPUT OPERATIONAL AMPLIFIERS
SLOS181B − FEBRUARY 1997 − REVISED APRIL 2004
67
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using PSpice
 Parts model generation software. The Boyle
macromodel (see Note 4) and subcircuit Figure 72 were generated using the TLE207x typical electrical and
operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters
can be generated to a tolerance of 20% (in most cases):
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
NOTE 4: G.R. Boyle, B.M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
.SUBCKT TLE2074 1 2 3 4 5
C1
11
12
2.2E−12
C2
6
7
10.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP VLN 0
+ 5.607E6 −6E6 6E6 6E6 −6E6
GA
6
0
11 12 333.0E−6
GCM
0
6
10 99 7.43E−9
ISS
3
10
DC 400.0E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
RD1
4
11
3.003E3
RD2
4
12
3.003E3
R01
8
5
80
R02
7
99
80
RP
3
4
27.30E3
RSS
10
99
500.0E3
VB
9
0
DC 0
VC
3
53
DC 2.20
VE
54
4
DC 2.20
VLIM
7
8
DC 0
VLP
91
0
DC 45
VLN
0
92
DC 45
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=15.00E−12 BETA=554.5E−6
+ VTO=−.6)
.ENDS
VCC +
RP
IN −
2
IN+
1
VCC −
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
VE
54
DE
DP
VC
DC
C1
53
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
4
R2
6
9
100.0E3
Figure 72. Boyle Macromodel and Subcircut
PSpice and Parts are trademarks of MicroSim Corporation.



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