LTC4150CMS datasheet(4/12 Pages) LINER

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LTC4150

4150fa

PI FU CTIO S

SENSE+ (Pin 1): Positive Sense Input. This is the

noninverting current sense input. Connect SENSE+ to the

load and charger side of the sense resistor. Full-scale

current sense input is 50mV. SENSE+ must be within

60mV of VDD for proper operation.

SENSE– (Pin 2): Negative Sense Input. This is the inverting

current sense input. Connect SENSE– to the positive

battery terminal side of the sense resistor. Full-scale

current sense input is 50mV. SENSE– must be within

60mV of VDD for proper operation.

CF+ (Pin 3): Filter Capacitor Positive Input. A capacitor

connected between CF+ and CF– filters and averages noise

and fast battery current variations. A 4.7µF value is recom-

mended. If filtering is not desired, leave CF+ and CF–

unconnected.

CF– (Pin 4): Filter Capacitor Negative Input. A capacitor

connected between CF+ and CF– filters and averages noise

and fast battery current variations. A 4.7µF value is recom-

mended. If filtering is not desired, leave CF+ and CF–

unconnected.

SHDN (Pin 5): Shutdown Digital Input. When asserted

low, SHDN forces the LTC4150 into its low current con-

sumption power-down mode and resets the part. In appli-

cations with logic supply VCC > VDD, a resistive divider

must be used between SHDN and the logic which drives it.

See the Applications Information section.

POL (Pin 6): Battery Current Polarity Open-Drain Output.

POL indicates the most recent battery current polarity

when INT is high. A low state indicates the current is

flowing out of the battery while high impedance means the

current is going into the battery. POL latches its state when

INT is asserted low. POL is an open-drain output and can

be pulled up to any logic supply up to 9V. In shutdown,

POL is high impedance.

GND (Pin 7): Ground. Connect directly to the negative

battery terminal.

VDD (Pin 8): Positive Power Supply. Connect to the load

and charger side of the sense resistor. SENSE+ also

connects to VDD. VDD operating range is 2.7V to 8.5V.

Bypass VDD with 4.7µF capacitor.

CLR (Pin 9): Clear Interrupt Digital Input. When asserted

low for more than 20µs, CLR resets INT high. Charge

counting is

unaffected. INT may be directly connected to

CLR. In this case the LTC4150 will capture each assertion

of INT and wait at least 1µs before resetting it. This ensures

that INT pulses low for at least 1µs but gives automatic INT

reset. In applications with a logic supply VCC > VDD, a

resistive divider must be used between INT and CLR. See

the Applications Information section.

INT (Pin 10): Charge Count Interrupt Open-Drain Output.

INT latches low every 1/(VSENSE • GVF) seconds and is

reset by a low pulse at CLR. INT is an open-drain output

and can be pulled up to any logic supply of up to 9V. In

shutdown INT is high impedance.

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