853031AY

www.icst.com/products/hiperclocks.html

REV. B SEPTEMBER 16, 2004

9

Integrated

Circuit

Systems, Inc.

ICS853031

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V

generated by the bias resistors R1, R2 and C1.This bias circuit

should be located as close as possible to the input pin. The ratio

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

drive 50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 3A and 3B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

R2

1K

V

CC

CLK_IN

+

-

R1

1K

C1

0.1uF

V_REF