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VSC7511 数据表(PDF) 40 Page - Microsemi Corporation |
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VSC7511 数据表(HTML) 40 Page - Microsemi Corporation |
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40 / 324 page  Functional Descriptions VMDS-10488 VSC7511 Datasheet Revision 4.2 25 Far-End Fault facility. In 100BASE-FX, the PCS supports the optional Far-End Fault facility. Both Far- End Fault generation (PCS_FX100_CFG.FEF_GEN_ENA) and Far-End Fault Detection (PCS_FX100_CFG.FEF_CHK_ENA) are supported. An Far-End Fault incident is recorded in PCS_FX100_STATUS.FEF_FOUND. Signal Detect. 100BASE-FX has a similar signal detect scheme to the SGMII and SerDes modes. For 100BASE-FX, PCS_FX100_CFG.SD_ENA enables signal detect, PCS_FX100_CFG.SD_POL controls the polarity, and PCS_FX100_CFG.SD_SEL selects the input source. The current status of the signal detect input can be observed through PCS_FX100_STATUS.SIGNAL_DETECT. For more information about signal detect, see Signal Detect, page 23. Link Surveillance. The PCS synchronization status can be observed through PCS_FX100_STATUS.SYNC_STATUS. When synchronization is lost, the link breaks and PCS_FX100_STATUS.SYNC_LOST_STICKY is set. The PCS continuously tries to recover the link. Unidirectional mode. 100BASE-FX has a similar unidirectional mode as SGMII and SerDes modes. PCS_FX100_CFG.UNIDIR_MODE_ENA enables unidirectional mode. 3.3 SERDES1G SERDES1G is a high-speed SerDes interface that operates at 1 Gbps (SGMII/SerDes) and 100 Mbps (100BASE-FX). The 100BASE-FX mode is supported by oversampling. The following table lists the registers associated with SERDES1G. For increased performance in specific application environments, SERDES1G supports the following: • Programmable loop-bandwidth and phase regulation of deserializer • Input buffer signal detect/loss of signal (LOS) options • Input buffer with equalization • Programmable output buffer features, including: • De-emphasis • Amplitude drive levels • Slew rate control • Idle mode • Synchronous Ethernet support • Loopbacks for system test 3.3.1 SERDES1G Basic Configuration The SERDES1G is enabled in SERDES1G_COMMON_CFG.ENA_LANE. By default, the SERDES1G is held reset and must be released from reset before the interface is active. This is done through SERDES1G_COMMON_CFG.SYS_RST and SERDES1G_MISC_CFG.LANE_RST. 3.3.1.1 SERDES1G Frequency Configuration To operate the SERDES1G block at 1.25 GHz (corresponding to 1 Gbps data rate), the internal macro PLL must be configured as follows: Table 14 • SERDES1G Registers Registers Description Replication SERDES1G_COMMON_CFG Common configuration Per SerDes SERDES1G_DES_CFG Deserializer configuration Per SerDes SERDES1G_IB_CFG Input buffer configuration Per SerDes SERDES1G_SER_CFG Serializer configuration Per SerDes SERDES1G_OB_CFG Output buffer configuration Per SerDes SERDES1G_PLL_CFG PLL configuration Per SerDes SERDES1G_MISC_CFG Miscellaneous configuration Per SerDes |
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