HMA82GS6AFR8N-UH datasheet(5/73 Pages) HYNIX

5 / 73 page

Rev. 1.4 / Sep.2017

Pin Descriptions

1. RAS_n is a multiplexed function with A16.

2. CAS_n is a multiplexed function with A15.

3. WE_n is a multiplexed function with A14.

Pin Name

Description

Pin Name

Description

A0-A16

SDRAM address bus

SCL

I2C serial bus clock for SPD/TS

BA0, BA1

SDRAM bank select

SDA

I2C serial bus data line for SPD/TS

BG0, BG1

SDRAM bank group select

SA0-SA2

I2C slave address select for SPD/TS

RAS_n1

SDRAM row address strobe

PARITY

SDRAM parity input

CAS_n2

SDRAM column address strobe

VDD

SDRAM I/O & core power supply

WE_n3

SDRAM write enable

VPP

SDRAM activating power supply

CS0_n, CS1_n,

CS2_n, CS3_n

Rank Select Lines

C0, C1

Chip ID lines for 3DS components

CKE0, CEK1

SDRAM clock enable lines

VREFCA

SDRAM command/address reference

supply

ODT0, ODT1

SDRAM on-die termination control lines

VSS

Power supply return (ground)

ACT_n

SDRAM activate

VDDSPD

Serial SPD/TS positive power supply

DQ0-DQ63

DIMM memory data bus

ALERT_n

SDRAM ALERT_n

CB0-CB7

DIMM ECC check bits

DQS0_t-DQS8_t

SDRAM data strobes

(positive line of differential pair)

RESET_n

Set SDRAMs to a Known State

DQS0_c-DQS8_c

SDRAM data strobes

(negative line of differential pair)

EVENT_n

SPD signals a thermal event has

occurred

DM0_n-DM8_n,

DBI0_n-DBI8_n

SDRAM data masks/data bus inversion

(x8-based x72 DIMMs)

VTT

Termination supply for the Address,

Command and Control bus

CK0_t, CK1_t

SDRAM clocks (positive line of differen-

tial pair)

No connection

CK0_c, CK1_c

SDRAM clocks (negative line of differ-

ential pair)

HMA82GS6AFR8N-UH 数据表(PDF) 5 Page - Hynix Semiconductor

HMA82GS6AFR8N-UH 数据表(HTML) 5 Page - Hynix Semiconductor

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