LSM303CTR datasheet(20/53 Pages) STMICROELECTRONICS

20 / 53 page

Functionality

LSM303C

20/53

DocID024975 Rev 2

A watermark interrupt CTRL_REG3_A (INT_XL_FTH) can be enabled in order to read data

from the FIFO and leave a free memory slot for incoming data. Setting the FIFO_CTRL

(FTH [4:0]) to an N value, the number of X, Y and Z data samples that should be read at the

rise of the watermark interrupt, in order to read the entire content of the FIFO, is N + 1.

4.2.4

Stream-to-FIFO mode

In Stream-to-FIFO mode (FIFO_CTRL(FMODE2:0) = 011), FIFO behavior changes

according to the IG_SRC1_A (IA) bit. When the IG_SRC1_A(IA) bit is equal to '1', FIFO

operates in FIFO mode, when the IG_SRC1_A (IA) bit is equal to '0', FIFO operates in

Stream mode.

The interrupt generator 1 should be set to the desired configuration by means of

IG_CFG1_A, IG_THS_X1_A, IG_THS_Y1_A and IG_THS_Z1_A.

The CTRL_REG7_A (LIR1) bit should be set to '1' in order to have latched interrupt.

4.2.5

Bypass-to-Stream mode

In Bypass-to-Stream mode (FIFO_CTRL (FMODE [2:0]) = '100'), X, Y and Z measurement

storage inside FIFO operates in Stream mode when the IG_SRC1_A (IA) is equal to '1',

otherwise FIFO content is reset (Bypass mode).

The interrupt generator 1 should be set to the desired configuration by means of

IG_CFG1_A, IG_THS_X1_A, IG_THS_Y1_A and IG_THS_Z1_A.

The CTRL_REG7_A (LIR1) bit should be set to '1' in order to have latched interrupt.

4.2.6

Bypass-to-FIFO mode

In Bypass-to-FIFO mode (FIFO_CTRL (FMODE [2:0]) = '111', FIFO behavior changes

according to the IG_SRC1_A(IA) bit. When the IG_SRC1_A(IA) bit is equal to '1,' FIFO

operates in FIFO mode. When the IG_SRC1_A(IA) bit is equal to '0', FIFO operates in

Bypass mode (FIFO content reset). If a latched interrupt is generated, FIFO starts collecting

data until the first data into the FIFO buffer is overwritten. The interrupt generator 1 should

be set to the desired configuration by means of IG_CFG1_A, IG_THS_X1_A,

IG_THS_Y1_A and IG_THS_Z1_A.

The CTRL_REG7_A (LIR1) bit should be set to '1' in order to have latched interrupt.

4.2.7

Retrieving data from FIFO

FIFO data is read from the OUT_X_A, OUT_Y_A and OUT_Z_A registers. A read operation

using a serial interface of the OUT_X_A, OUT_Y_A or OUT_Z_A output registers provides

the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z

data are placed in the OUT_X_A, OUT_Y_A and OUT_Z_A registers and both single read

and read_burst operations can be used.

4.2.8

FIFO multiple read (burst)

Starting from Addr 28h multiple reads can be performed. Once the read reaches Addr 2Dh

the system automatically restarts from Addr 28h.

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