25/30

L6997S

Figure 25. Efficiency Vs Output Current

Figure 26. Efficiency Vs Output Current

50

55

60

65

70

75

80

85

90

95

100

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Output Current [A]

VOUT = 12V

VIN = 25V

VCC = 5V

FSW = 200KHz

VOUT = 5V

VOUT = 3.3V

0

10

20

30

40

50

60

70

80

90

100

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Output Current [A]

VOUT = 12V

VIN = 33V

7.5 DDR MEMORY AND TERMINATION SUPPLY

Double data rate (DDR) memories require a particular Power Management Architecture. This is due to fact that

the trace between the driving chipset and the memory input must be terminated with resistors. Since the Chipset

driving the Memory has a push pull output buffer, the Termination voltage must be capable of sourcing and sink-

ing current. Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the

memory is a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory

Supply is 2.5V and the Termination voltage is 1.25Vwhile for the DDRII the Memory Supply is 1.8V and the Ter-

mination voltage is 0.9V. Figure 27 shows a complete DDRII Memory and Termination Supply realized by using

2 x L6997S. The 1.8V section is powering the memory, while the 0.9V section is providing the termination voltage.

Figure 27. Application Idea: DDRII Memory Supply

L6997

PGND

PHASE

GNDSENSE

VSENSE

LGATE

BOOT

HGATE

VCCDR

FB

OSC

VCC

VREF

NOSKIP

OVP

PGOOD

SHDN

VCC

L6997

GND

SS

ILIM

U2

GNDSENSE

VSENSE

FB

PGND

LGATE

PHASE

HGATE

BOOT

VCCDR

VCC

OSC

NOSKIP

INT

VREF

SHDN

PGOOD OVP GND

U1

SS

ILIM

VIN

VCC

INT

+

-

CHIPSET

MEMORY

SUPPLY

BUS

TERMINATION

NETWORK

Vddq

1.8V@15A

Vtt

0.9V@- 5A

+

R

2R

2R

R

STS8DNF3LL

STS11NF3LL

STS11NF3LL

L6997S

L6997S