AD8099ACPZ-R2 datasheet(21/28 Pages) AD

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AD8099

Rev. B | Page 21 of 28

GAIN FROM

"B" TO OUTPUT

=–

GAIN FROM

"A" TO OUTPUT

NOISE GAIN =

NG = 1 +

IN–

VN, R1

VN, R3

IN+

4kTR2

4kTR1

4kTR3

VN, R2

VN2 + 4kTR3 + 4kTR1

R1 + R2

IN+2R32 + IN–2

R1 × R2

+ 4kTR2

R1 + R2

RTI NOISE =

RTO NOISE = NG × RTI NOISE

VOUT

Figure 69. Op Amp Noise Analysis Model

In applications where noise sensitivity is critical, care must be

taken not to introduce other significant noise sources to the

amplifier. Each resistor is a noise source. Attention to the

following areas is critical to maintain low noise performance:

design, layout, and component selection. A summary of noise

performance for the amplifier and associated resistors can be

seen in Table 4.

INPUT BIAS CURRENT AND DC OFFSET

In high noise gain configurations, the effects of output offset

voltage can be significant, even with low input bias currents and

input offset voltages. Figure 70 shows a comprehensive offset

voltage model, which can be used to determine the referred to

output (RTO) offset voltage of the amplifier or referred to input

(RTI) offset voltage.

GAIN FROM

"B" TO OUTPUT

=–

GAIN FROM

"A" TO OUTPUT

NOISE GAIN =

NG = 1 +

IB–

VOS

IB+

OFFSET (RTO) = VOS 1 +

+ IB+ × R3 1 +

– IB– × R2

OFFSET (RTI) = VOS + IB+ × R3 – IB–

R1 × R2

R1 + R2

OFFSET (RTI) = VOS

IF IB+ = IB– AND R3 =

R1 × R2

R1 + R2

VOUT

FOR BIAS CURRENT CANCELLATION:

Figure 70. Op Amp Total Offset Voltage Model

For RTO calculations, the input offset voltage and the voltage

generated by the bias current flowing through R3 are multiplied

by the noise gain of the amplifier. The voltage generated by IB–

through R2 is summed together with the previous offset

voltages to arrive at a final output offset voltage. The offset

voltage can also be referred to the input (RTI) by dividing the

calculated output offset voltage by the noise gain.

As seen in Figure 70 if IB+ and IB– are the same and R3 equals the

parallel combination of R1 and R2, then the RTI offset voltage

can be reduced to only VOS. This is a common method used to

reduce output offset voltage. Keeping resistances low helps to

minimize offset error voltage and keeps the voltage noise low.

DISABLE PIN AND INPUT BIAS CANCELLATION

The AD8099 DISABLE pin performs three functions; enable,

disable, and reduction of the input bias current. When the

DISABLE pin is brought to within 0.7 V of the positive supply,

the input bias current is reduced by an approximate factor of 60.

However, the input current noise doubles to 5.2 pA/√Hz. Table

5 outlines the DISABLE pin functionality.

Table 5. DISABLE Pin Truth Table

Supply Voltage

±5 V

+5 V

Disable

–5 to +2.4

0 to 2.4

Enable

Open

Low Input Bias Current

4.3 to 5

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