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AS7C251MPFD18A

2/10/05, v. 1.2

Alliance Semiconductor

4 of 19

Functional description

The AS7C251MPFD18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as

1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.

(CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the

processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven

on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address

strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use an interleaved

count sequence. With LBO driven LOW, the device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting

BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers are disabled

when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is

incremented internally to the next burst address if BWn and ADV are sampled LOW. This device operates in double-cycle deselect feature

during read cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are

as follows:

•ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

•

The AS7C251MPFD18A family

pin TQFP package.

TQFP capacitance

* Guaranteed not tested

TQFP thermal resistance

Parameter

Symbol

Test conditions

Min

Max

Unit

Input capacitance

-

5

pF

I/O capacitance

-

7

pF

Description

Conditions

Symbol

Typical

Units

Thermal resistance

1 This parameter is sampled

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer

40

°C/W

4–layer

22

°C/W

Thermal resistance

8

°C/W