AS7C252MPFS18A datasheet(15/18 Pages) ALSC

15 / 18 page

2/14/05, v.1.3

Alliance Semiconductor

15 of 18

AS7C252MPFS18A

AC test conditions

Notes

For test conditions, see “AC test conditions”, Figures A, B, and C.

This parameter is measured with output load condition in Figure C.

This parameter is sampled but not 100% tested.

4tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.

5tCH is measured as high if above VIH, and tCL is measured as low if below VIL.

This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times for all rising edges of CLK when chip is enabled.

Write refers to GWE, BWE, and BW[a,b].

Chip select refers to CE0, CE1, and CE2.

Z0 = 50Ω

DOUT

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+2.5V

• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.

• Input pulse level: GND to 2.5V. See Figure A.

• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.25V.

VL = VDDQ/2

Thevenin equivalent:

353

Ω/1538Ω

5 pF*

319

Ω/1667Ω

DOUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

+2.5V

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