AS7C331MNTD18A datasheet(15/18 Pages) ALSC

15 / 18 page

AS7C331MNTD18A

12/24/04, v 2.7

Alliance Semiconductor

P. 15 of 18

AC test conditions

Notes:

1) For test conditions, see “AC test conditions”, Figures A, B, C

2) This parameter measured with output load condition in Figure C.

3) This parameter is sampled, but not 100% tested.

4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.

5) tCH measured high above VIH and tCL measured as low below VIL

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

7) Write refers to R/W and BW[a,b]

8) Chip select refers to CE0, CE1, and CE2.

Z0 = 50Ω

DOUT

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

VL = 1.5V

for 3.3V I/O;

= VDDQ/2

for 2.5V I/O

Thevenin equivalent:

353

Ω/1538Ω

5 pF*

319

Ω/1667Ω

DOUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

+3.3V for 3.3V I/O;

/+2.5V for 2.5V I/O

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