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AS7C331MPFD32A 数据表(PDF) 1 Page - Alliance Semiconductor Corporation

部件名 AS7C331MPFD32A
功能描述  3.3V 1M x 32/36 pipelined burst synchronous SRAM
PDF  19 Pages
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制造商  ALSC [Alliance Semiconductor Corporation]
网页  https://www.alliancememory.com
标志 ALSC - Alliance Semiconductor Corporation

AS7C331MPFD32A 数据表(HTML) 1 Page - Alliance Semiconductor Corporation

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February 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C331MPFD32A
AS7C331MPFD36A
2/10/05, v.1.1
Alliance Semiconductor
1 of 19
3.3V 1M
× 32/36 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.1/3.5/3.8 ns
•Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Selection guide
-200
-166
-133
Units
Minimum cycle time
5
6
7.5
ns
Maximum clock frequency
200
166
133
MHz
Maximum clock access time
3.1
3.5
3.8
ns
Maximum operating current
450
400
350
mA
Maximum standby current
170
150
140
mA
Maximum CMOS standby current (DC)
90
90
90
mA
A[19:0]
20
18
20
20
Q0
Q1
1M × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQd
CLK
DQ
Byte write
registers
register
DQc
CLK
DQ
Byte write
registers
DQb
CLK
DQ
Byte write
registers
DQa
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a:d]
4
32/36
GWE
BWE
BWd
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BWc
BWb
BWa
OE
ZZ
LBO
OE
CLK
CLK
32/36
32/36
2
2


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