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LP3985 数据表(PDF) 5 Page - Lowpower Semiconductor inc |
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LP3985 数据表(HTML) 5 Page - Lowpower Semiconductor inc |
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5 / 7 page ![]() LP3985-00 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 5 of 7 Preliminary Datasheet LP3985 Applications Information Like any low-dropout regulator, the external capacitors used with the LP3985 must be carefully selected for regulator stability and performance. Using a capacitor whose value is > 1µF on the LP3985 input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The LP3985 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1µF with ESR is > 25mΩ on the LP3985 output ensures stability. The LP3985 still works well with output capacitor of other types due to the wide stable ESR range. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the LP3985 and returned to a clean analog ground. Thermal Considerations Thermal protection limits power dissipation in LP3985. When the operation junction temperature exceeds 150℃, the OTP circuit starts the thermal shutdown function turn the pass element off. The pass element turns on again after the junction temperature cools by 20℃. For continue operation, do not exceed absolute maximum operation junction temperature 125℃. The power dissipation definition in device is: PD = (VIN−VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) − TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125℃, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. |
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