LP4065-00

Aug.-2018

www.lowpowersemi.com

Page 2 of 8

Preliminary Datasheet

LP4065

Functional Pin Description

Package Type

Pin Configurations

LP4065AB6F

LP4065PB6F

SOT23-6

5

1

3

6

4

EN

2

GND

CHRG

ISET

BAT

VIN

5

1

3

6

4

PG

2

GND

CHRG

ISET

BAT

VIN

Pin Description

No.

NAME

DESCRIPTION

LP4065A

LP4065P

1

EN

Charge Enable Input (active low).

PG

Open-Drain Status Output. Low indicates the input voltage is above UVLO and

the OUT (battery) voltage.

2

GND

GND is the connection to system ground.

3

CHRG

Open-Drain Charge Status Output. When the battery is charging, the CHRG pin

is pulled low by an internal NMOS. When the charge cycle is completed, the pin

could be pulled High by an external pull high resistor.

4

VIN

VIN is the input power source. Connect to a wall adapter.

5

BAT

BAT is the connection to the battery. Typically a 10µF Tantalum capacitor is

needed for stability when there is no battery attached. When a battery is

attached, only a 1uF ceramic capacitor is required.

6

ISET

Charge Current Program. The charge current is programmed by connecting a