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LP4075 数据表(PDF) 6 Page - Lowpower Semiconductor inc |
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LP4075 数据表(HTML) 6 Page - Lowpower Semiconductor inc |
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6 / 7 page ![]() LP4075-00 Aug.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 6 of 7 Preliminary Datasheet LP4075 Thermal Limit An internal thermal feedback loop reduces the programmed charge current if the die temperature attempts to rise above a preset value of approximately 125℃. This feature protects the LP4075 from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the LP4075. The charge current can be set according to typical (not worst-case) ambient temperature with the assurance that the charger will automatically reduce the current in worst-case conditions. Automatic Recharge Once the charge cycle is terminated, the LP4075 continuously monitors the voltage on the BAT pin using a comparator with a 2ms filter time (TRECHARGE). A charge cycle restarts when the battery voltage falls below 4.0V (which corresponds to approximately 80% to 90% battery capacity). This ensures that the battery is kept at or near a fully charged condition and eliminates the need for periodic charge cycle initiations. CHRG output enters a strong pull-down state during recharge cycles. Power Dissipation The conditions that cause the LP4075 to reduce charge current through thermal feedback can be approximated by considering the power dissipated in the IC. Nearly all of this power dissipation is generated by the internal MOSFET—this is calculated to be approximately: PD=(VIN-VBAT) × IBAT VIN Bypass Capacitor Many types of capacitors can be used for input bypassing; however, caution must be exercised when using multilayer ceramic capacitors. Because of the self-resonant and high Q characteristics of some types of ceramic capacitors, high voltage transients can be generated under some start-up conditions, such as connecting the charger input to a live power source. Adding a 1.5Ω resistor in series with an X5R ceramic capacitor will minimize start-up voltage transients. Layout Considerations For the main current paths as indicated in bold lines, keep their traces short and wide. Put the input capacitor as close as possible to the device pins (VIN and GND). Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. |
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