®

AS7C331MPFS18A

12/23/04, v 2.6

Alliance Semiconductor

16 of 19

AC test conditions

Notes

1

For test conditions, see “AC Test Conditions”, Figures A, B, and C.

2

This parameter is measured with output load condition in Figure C.

3

This parameter is sampled but not 100% tested.

6

This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times for all rising edges of CLK when chip is enabled.

7

Write refers to GWE, BWE, and BW[a,b]

.

8

Chip select refers to CE0, CE1, and CE2.

50

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

for 3.3V I/O;

for 2.5V I/O

Thevenin equivalent:

353

Ω/1538Ω

5 pF*

319

Ω/1667Ω

GND

Figure C: Output load(B)

*including scope

and jig capacitance

+3.3V for 3.3V I/O;

/+2.5V for 2.5V I/O