W7500P datasheet(37/38 Pages) WIZNET

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Document History Information

Version

Date

Descriptions

Ver. 1.0.0

18SEP2017

Initial Release

Ver. 1.0.1

26OCT2017

Fixed value Driving Strength condition in PADCON.

Ver. 1.0.2

09NOV2017

Fixed Typo I/O Pad Characteristics VOL description (high -> low)

Ver. 1.0.3

30NOV2017

Fixed figure 8. (W7500P Pin out)

Ver. 1.0.4

18DEC2017

Add Reset & PLL characteristics.

Ver. 1.0.5

30JAN2018

1. Fixed figure 8 (W7500P Pin layout) / Added subhead (4.2.1

W7500, 4.2.2 W7500P) / Fixed table 8(modified Symbol name)

2. Modified SRAM description (2. Description)

Ver. 1.0.6

05FEB2018

Add info about W7500P power consumption.(Current Characteristics)

Ver. 1.0.7

27JUL2018

Fixed figure 2. CRG Diagram (Input Information of WDOGCLK, TIMCLK0,

TIMCLK1).

Ver. 1.0.8

17OCT2018

Fixed Power Supply description (271V ~ 5.5V -> 2.7V ~ 3.6V)

Ver. 1.0.9

12NOV2019

Fixed 5.2

I/O Power on slope (5V/sec -> 3.3V)

The ADC causes the interference between channels. So all

explain of ADC are removed

Ver 1.1.0

20DEC2019

Fixed 3.17 UART speed to 460.8 Kbit/s from 3 Mbit/s.

W7500P 数据表(PDF) 37 Page - WIZnet Co., Ltd

W7500P 数据表(HTML) 37 Page - WIZnet Co., Ltd

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