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IS25LP064A-RBLE 数据表(PDF) 70 Page - Integrated Silicon Solution, Inc

部件名 IS25LP064A-RBLE
功能描述  3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  99 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LP064A-RBLE 数据表(HTML) 70 Page - Integrated Silicon Solution, Inc

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IS25LP064A/032A
Integrated Silicon Solution, Inc.- www.issi.com
70
Rev. A
11/06/2015
8.36 FAST READ DTR MODE OPERATION (FRDTR, 0Dh)
The FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling edge
of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both
rising and falling edge of SCK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock,
and 2-bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the
falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR instruction. The
address counter rolls over to 0 when the highest address is reached.
The sequence of issuing FRDTR instruction is: CE# goes low  Sending FRDTR instruction code (1bit per
clock)  3-byte address on SI (2-bit per clock)  4 dummy clocks on SI  Data out on SO (2-bit per clock) 
End FRDTR operation via driving CE# high at any time during data out.
While a Program/Erase/Write Status Register cycle is in progress, FRDTR instruction will be rejected without
any effect on the current cycle.
Figure 8.55 FRDTR Sequence
CE #
SCK
SI
SO
Data Out 1
Instruction = 0Dh
CE #
SCK
SI
SO
3-byte Address
High Impedance
0
1
2
3
4
5
6
7
8
9
10
...
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
...
Mode 3
Mode 0
tV
23 22 21
0
7 6 5 4 3
2 1
0
Data Out 2
7 6 5 4 3
2 1
0
Data Out 3
7 6 5 4 3
2 1
0
4 Dummy
Cycles
20 19 18 17
...
Data Out ...
7 6 5 ...



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