IS25LP032D-RHLA3:P datasheet(95/118 Pages) ISSI

95 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.43 AUTOBOOT

SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command. And,

in order to read boot code from an SPI device, the host memory controller or processor must supply the read

command from a hardwired state machine or from some host processor internal ROM code.

Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to

start reading boot code.

The AutoBoot feature allows the host memory controller to take boot code from the device immediately after the

end of reset, without having to send a read command. This saves 32 or more cycles and simplifies the logic needed

to initiate the reading of boot code.

 As part of the Power-up Reset, Hardware Reset, or Software Reset process the AutoBoot feature automatically

starts a read access from a pre-specified address. At the time the reset process is completed, the device is

ready to deliver code from the starting address. The host memory controller only needs to drive CE# signal from

high to low and begin toggling the SCK signal. The device will delay code output for a pre-specified number of

clock cycles before code streams out.

– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by

the host.

– The host cannot send commands during this time.

– If QE bit (Bit 6) in the Status Register is set to “1”, Fast Read Quad I/O operation will be selected and initial

delay is the same as dummy cycles of Fast Read Quad I/O Read operation. If it is set to “0”, Fast Read

operation will be applied and initial delay is the same as dummy cycles of Fast Read operation. Maximum

operation frequency will be 133MHz for both operations.

 The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address

(ABSA) field of the AutoBoot Register.

– Data will continuously shift out until CE# returns high.

 At any point after the first data byte is transferred, when CE# returns high, the SPI device will reset to standard

SPI mode; able to accept normal command operations.

– A minimum of one byte must be transferred.

– AutoBoot mode will not initiate again until another power cycle or a reset occurs.

 An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.

The AutoBoot register bits are non-volatile and provide:

 The starting address set by the AutoBoot Start Address (ABSA).

 The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 4-bit count value.

IS25LP032D-RHLA3:P 数据表(PDF) 95 Page - Integrated Silicon Solution, Inc

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