IS25LP032D-RBLA3 datasheet(84/118 Pages) ISSI

84 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.39 FAST READ DTR MODE OPERATION IN SPI MODE (FRDTR, 0Dh)

The FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling edge of

clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both rising

and falling edge of SCK at a maximum frequency. The 2-bit address can be latched-in at one clock, and 2-bit data

can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the falling edge of

clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR instruction. The

address counter rolls over to 0 when the highest address is reached.

The sequence of issuing FRDTR instruction is: CE# goes low  Sending FRDTR instruction code (1bit per clock)

 3-byte address on SI (2-bit per clock)  8 dummy clocks (configurable, default is 8 clocks) on SI  Data out on

SO (2-bit per clock)  End FRDTR operation via driving CE# high at any time during data out.

While a Program/Erase/Write Status Register cycle is in progress, FRDTR instruction will be rejected without any

effect on the current cycle.

Figure 8.63 FRDTR Sequence In SPI Mode

CE #

SCK

Data Out 1

Instruction = 0Dh

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

23 22 21

7 6 5 4 3

2 1

Data Out 2

7 6 5 4 3

2 1

Data Out ...

7 6

8 Dummy Cycles

20 19 18 17

5 ...

...

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

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