MXT1664T3-ATESSQTP datasheet(21/98 Pages) MICROCHIP

21 / 98 page

MXT1664T3 2.0

 2018 Microchip Technology Inc.

DS40002054A-page 21

2.5

Schematic Notes

2.5.1

POWER SUPPLY

The sense and I/O pins are supplied by the power rails on the device as listed in Table 2-1. This information is also

indicated in “Pin configuration”.

2.5.2

DECOUPLING CAPACITORS

All decoupling capacitors must be X7R or X5R and placed less than 5 mm away from the pins for which they act as

bypass capacitors. Pins of the same type can share a capacitor provided no pin is more than 10 mm from the capacitor.

The schematics on the previous pages show the capacitors required. The parallel combination of capacitors is

recommended to give high and low frequency filtering, which is beneficial if the voltage regulators are likely to be some

distance from the device (for example, If an active tail design is used). Note that this requires that the voltage regulator

supplies for AVdd, Vdd and VddIO are clean and noise free. It also assumes that the track length between the capacitors

and on-board power supplies is less than 50 mm.

The number of base capacitors can be reduced if the pinout configuration means that sharing a bypass capacitor is

possible (subject to the distance between the pins satisfying the conditions above and there being no routing difficulties).

2.5.3

PULL-UP RESISTORS

The pull-up resistors shown in the schematics are suggested typical values and may be modified to meet the

requirements of an individual customer design.

This applies, in particular, to the pull-up resistors on the I2C SDA and SCL lines (shown on the schematic), as the values

of these resistors depends on the speed of the I2C interface. See Section 14.10 “I2C Specification” for details.

2.5.4

VOLTAGE BOOSTER

The XVdd power can be supplied using the Voltage Booster shown in Figure 2-1 on page 22 or an external regulated

supply. See Section 14.2 “Recommended Operating Conditions” for the supply voltages possible. Two frequency modes

are supported so that it is possible to avoid interference with other functions, such as Long-Term Evolution (LTE)

interference. Depending on the chosen frequency mode, a different inductor has to be used. The high frequency mode

requires a 10 µH inductor and a 47 µH inductor should be used in the low frequency mode.

If an external supply is used, the components in Figure 2-1 on page 22 can be omitted and VREGBOOST should be left

open circuit or connected to a test point. Connection to a test point is preferred and is recommended by Microchip.

TABLE 2-1:

POWER SUPPLY FOR SENSE AND I/O PINS

Power Supply

Pins

XVdd

X sense pins

AVdd

Y sense pins, DS0, VREGBOOST

VddIO

RESET, COMMSEL, CHG, I2CMODE

SCL, SDA, ADDSEL/USBDP, USBDM, NOISE_IN

TEST/DBG_SS, DBG_DATA/XTAL_XOUT, DBG_CLK/XTAL_XIN

GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5

Note that if a VddIO supply at the low end of the allowable range is used, the I2C pull-up resistor values may need to

be reduced.

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