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IS25LP016D-RGLA3 数据表(PDF) 84 Page - Integrated Silicon Solution, Inc

部件名 IS25LP016D-RGLA3
功能描述  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  114 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LP016D-RGLA3 数据表(HTML) 84 Page - Integrated Silicon Solution, Inc

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IS25LP016D
IS25WP016D
Integrated Silicon Solution, Inc.- www.issi.com
84
Rev. B10
03/09/2020
Figure 8.67 FRQDTR Sequence (with command decode cycles)
CE #
SCK
Instruction = EDh
CE #
SCK
3-byte Address
High Impedance
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
...
Mode 3
Mode 0
tV
20 16 12
5 1
21 17 13
Data
Out
4 0
IO0
IO1
IO0
22 18 14
23 19 15
8 4
0
9 5
1
10 6
2
11 7
3
6 Dummy Cycles
IO2
IO3
IO1
IO2
IO3
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
Data
Out
13
5 1
4 0
6 2
7 3
Mode Bits
...
...
...
...
Notes:
1. If the mode bits=AXh (
where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles are
same, then X should be Hi-Z.



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