IS25LP016D-RHLA3 datasheet(8/114 Pages) ISSI

8 / 114 page

IS25LP016D

IS25WP016D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B10

03/09/2020

Top View, Balls Facing Down

RESET#(NC)

SCK

GND

VCC

CE#

WP#(IO2)

SO(IO1)

SI(IO0)

HOLD# or

RESET# (IO3)

(3)

(1,2)

24-ball TFBGA, 4x6 Ball Array (Package:G)

RESET#/(NC)

SCK

GND

VCC

CE#

WP#(IO2)

SO(IO1)

SI(IO0)

HOLD# or

RESET# (IO3)

Top View, Balls Facing Down

24-ball TFBGA, 5x5 Ball Array (Package:H)

(3)

(1,2)

Notes:

The pin can be configured as Hold# or Reset# by setting P7 bit of the Read Register. Pin default is Hold#.

Dedicated RESET# pin is available in devices with a dedicated part number, in these devices Pin 1 (16-pin

SOIC) or ball D4 (24-ball TFBGA) are set to Hold# regardless of P7 setting of the Read Register.

For compatibility, the pin can be disabled on dedicated part numbers by setting Bit0 (Dedicated RESET#

Disable) of the Function Register to “1” (default is “0” from factory on dedicated part numbers). An internal

pull-up resistor exists and the pin may be left floating if not used.

16-pin SOIC / 24-ball TFBGA

Device with HOLD#/RESET#

Device with dedicated RESET#

Pin1 / Ball D4

Hold#(IO3) or RESET#(IO3) by P7 bit setting

Hold#(IO3) only regardless of P7 bit setting

Pin3 / Ball A4

RESET#

Part Number Option

R or P

IS25LP016D-RHLA3 数据表(PDF) 8 Page - Integrated Silicon Solution, Inc

IS25LP016D-RHLA3 数据表(HTML) 8 Page - Integrated Silicon Solution, Inc

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