For systems using single-ended input ADCs to convert the analog output voltage into digital, Figure 8-3 shows

an example of a TLV313-Q1 based signal conversion and filter circuit. With R1 = R2 = R3 = R4, the output

requirement of the system and use NP0-type capacitors for best performance. For most applications, R1 = R2 =

R3 = R4 = 10 kΩ and C1 = C2 = 1000 pF yields good performance.

DCDC_OUT

DCDC_HGND

HLDO_IN

HLDO_OUT

HGND

INP

INN

NC

AMC3301-Q1

DCDC_IN

LDO_OUT

VDD

OUTP

OUTN

GND

DIAG

DCDC_GND

+

±

R4

R3

R1

R2

ADC

GND

GND

To MCU

C1

C2

GND

TLV313-Q1

Figure 8-3. Connecting the AMC3301-Q1 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of successive-

approximation-register (SAR) ADCs, see 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest

Distortion and Noise reference guide and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power

reference guide, available for download at www.ti.com.

8.2.4 Application Curve

In frequency inverter applications, the power switches must be protected in case of an overcurrent condition. To

allow for fast powering off of the system, a low delay caused by the isolated amplifier is required. Figure 8-4

shows the typical full-scale step response of the AMC3301-Q1. Consider the delay of the required window

comparator and the MCU to calculate the overall response time of the system.

VIN

VOUTP

VOUTN

Figure 8-4. Step Response of the AMC3301-Q1

www.ti.com

AMC3301-Q1

SBASA73 – JULY 2020

Copyright © 2020 Texas Instruments Incorporated

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