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AS7C33256PFS18B 数据表(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C33256PFS18B 数据表(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 19 page  December 2004 Copyright © Alliance Semiconductor. All rights reserved. AS7C33256PFS18B 3.3V 256K × 18 pipeline burst synchronous SRAM ® 12/10/04; v.1.7 Alliance Semiconductor P. 1 of 19 Features • Organization: 262,144 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns •Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and global write • Multiple chip enables for easy expansion • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ Selection guide –200 –166 –133 Units Minimum cycle time 5 6 7.5 ns Maximum clock frequency 200 166 133 MHz Maximum clock access time 3.0 3.5 4 ns Maximum operating current 375 350 325 mA Maximum standby current 130 100 90 mA Maximum CMOS standby current (DC) 30 30 30 mA Logic block diagram Burst logic ADV ADSC ADSP CLK LBO CLK CLR CS 18 16 18 A[17:0] 18 Address D Q CS CLK register 256K × 18 Memory array 18 18 DQb CLK DQ Byte Write registers DQa CLK DQ Byte Write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down 2 CE0 CE1 CE2 BWb BWa OE ZZ OE CLK CLK BWE GWE 18 DQ [a,b] |
类似零件编号 - AS7C33256PFS18B |
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类似说明 - AS7C33256PFS18B |
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