SARA-R5 series - Data sheet

UBX-19016638 - R06

Interfaces

Page 14 of 43

C1-Public

2.3.3 Module reset

SARA-R5 series modules can be reset (re-booted), saving current parameter settings in the module’s

non-volatile memory and performing a proper network detach, by:



AT+CFUN command (see the SARA-R5 series AT commands manual [1]). This causes a graceful

software reset of the module.

An abrupt software reset of the module is executed by applying a low pulse at the RESET_N input pin,

which is normally set high by an internal pull-up, for a valid time period (see section 4.2.7). The current

parameter settings are not saved in the module’s non-volatile memory and a proper network detach

is not performed.

The RESET_N line is intended to be driven by open drain, open collector or contact switch.

An abrupt emergency hardware reset of the modules, without storage of the current parameter

settings in the module’s non-volatile memory and without proper network detach procedure, can be

triggered by:



Forcing a low pulse at the PWR_ON input pin, for a valid time period (see section 4.2.6, module

abrupt emergency hardware reset)

2.4 SIM

2.4.1

SIM interface

SARA-R5 series modules provide on the VSIM, SIM_IO, SIM_CLK, SIM_RST pins an interface to

connect an external SIM card/chip. Both 1.8 V and 3.0 V SIM types are supported. Activation and

deactivation with an automatic voltage switch from 1.8 V to 3.0 V is implemented according to the

ISO-IEC 7816-3 specifications.

2.4.2 SIM detection

The GPIO5 pin of SARA-R5 series modules is a 1.8 V digital input which can be configured as an

external interrupt to detect the SIM card presence (as a feature which can be optionally used), as

intended to be properly connected to the mechanical switch of an external SIM card holder.

For more details, see the SARA-R5 series system integration manual [2] and the SARA-R5 series AT

commands manual [1].

2.5 Serial communication

The SARA-R5 series provides the following serial communication interfaces:



UART interfaces, available for communications with host application processor (2.5.1)



USB 2.0 compliant interface, available for diagnostics only (2.5.2)



SPI interfaces, available for communications with external SPI devices and for diagnostic (2.5.3)



SDIO interface, available for communications with external SDIO devices (2.5.4)



DDC (I2C bus compatible) interface, available for communications with external I2C devices (2.5.5)