ELD5016 datasheet(32/38 Pages) EMC

32 / 38 page

eLD5016

8-Bit Microcontroller



Product Specification (V1.0) 2.16.2017

(This specification is subject to change without prior notice)

5.6 Interrupt

The MCU has internal interrupts which are falling edge triggered, as follows: TCC timer

overflow interrupt (internal), two 8-bit counters overflow interrupt.

If these interrupt sources change signal from high to low, the RF register will generate

'1' flag to the corresponding register if IOCF register is enabled.

RF is the interrupt status register which records the interrupt request in flag bit. IOCF is

the interrupt mask register. Global interrupt is enabled by ENI instruction and is

disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it

will cause the next instruction to be fetched from Address 008H. Once in the interrupt

service routine, the source of the interrupt can be determined by polling the flag bits in

the RF register. The interrupt flag bit must be cleared in the software before leaving the

interrupt service routine and enabling interrupts to avoid recursive interrupts.

There are four external interrupt pins including INT0, INT1, INT2, and INT3. And four

internal counter interrupts available.

Signals of external interrupt INT0, INT1, INT2, and INT3 are from Port 7 Bit 0 to Bit 3. If

IOCF is enabled, these signals will cause an interrupt, or these signals will be treated

as general input data.

After reset, the next instruction will be fetched from Address 000H, the Instruction

Interrupt is 001H and the Hardware Interrupt is 008H.

TCC will go to Address 0x08 in Green mode or Normal mode after time out.

These two cases will set the RF flag.

ELD5016 数据表(PDF) 32 Page - ELAN Microelectronics Corp