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MCP47CMB21 数据表(PDF) 81 Page - Microchip Technology |
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MCP47CMB21 数据表(HTML) 81 Page - Microchip Technology |
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81 / 124 page  2018-2019 Microchip Technology Inc. DS20006089B-page 81 MCP47CXBXX FIGURE 7-6: I2C ACK/NACK Behavior (Read Command Example). Read 1 Word Command S Slave Address Command Master S 01 1 Slave Address Data Byte Data Byte P Master (Continued) 11 1 1P Example 1 (No Command Error) Master S 1100000 0 1 0 0 0 0 1 1 1 x 1 MCP47CXBXX 00 I2C Bus S 110000 0 0 0 0 0 0 0 0 1 1 x 0 Master (Continued) S 00 00 1 0 0 1 1 1 1 P MCP47CXBXX (Continued) 0 d d d d d d d d 0 dddddddd 0 I2C Bus (Continued) S 0 0 0 0 0 0 0 1 0 d d d d d d d d 0 dddddddd 0 P Example 2 (Command Error) Master S 1100000 0 1 0 1 1 1 1 0 0 x 1 MCP47CXBXX 01 I2C Bus S 1100000 0 0 0 1 1 1 1 0 0 x 1 Master (Continued) S 11 00 0 0 0 1 1 1 1 P MCP47CXBXX (Continued) 0 ? ? ? ? ? ? ? ? 0 ???????? 1 I2C Bus (Continued) S 1 1 0 0 0 0 0 1 0 ? ? ? ? ? ? ? ? 0 ???????? 1 P Note 1: Once a command error has occurred (Example 2), the MCP47CXBXX will NACK until a Start condition occurs. 2: For command error case (Example 2), the data read is from the register of the last valid address loaded into the device. |
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