Silicom Ltd. Connectivity Solutions

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Packet interrupt coalescing timers (packet timers) and absolute-delay interrupt timers for both transmit and receive operation

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EEE (IEEE 802.3az) for reduced power consumption during low link utilization periods

Common Key features:

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PCI Express ExpressModule Electromechanical Specification Revision 1.0

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Support PCI Express Base Specification 2.1 (5 GTs)

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High performance, reliability, and low power use in Intel i350 Quad integrated MAC + PHY and SERDES chip Controllers

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Ultra deep, packet buffer per channel lowers CPU utilization

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Hardware acceleration that can offload tasks from the host processor. The Controllers can offload TCP/UDP/IP checksum

calculations and TCP segmentation

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Server class reliability, availability and performance features:

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Link Aggregation and Load Balancing

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Priority queuing

– 802.1p layer 2 priority encoding

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Virtual LANs

–802.1q VLAN tagging

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Jumbo Frame (9.5KB)

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802.x flow control

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Multicast/ broadcast Packet replication

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Supports Vital Product Data (VPD)

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LEDs indicators for link/Activity Mode status

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Hot Plug not supported. Can be supported by assembly change

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LEDs indicators for link/Activity/Bypass Mode status

Technical Specifications

Bypass Specifications

WDT Interval (Software

Programmable):

3,276,800 mSec (3,276.8 Sec): Maximum

100 mSec ( 0.1 Sec) : Minimum

WDT Interval = (2^wdt_interval_parameter)*(0.1) sec.

wdt_interval_parameter: { Valid Range: 0-15}

Copper Gigabit Ethernet Technical Specifications

– (1000Base-T) Adapters:

IEEE Standard / Network

topology:

Gigabit Ethernet, 1000Base-T

Fast Ethernet, 100Base-TX

Ethernet, 10Base-T

Full duplex / Simplex

Support both Simplex & Full duplex operation in all operating speeds